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Telfor Journal
2017, vol. 9, br. 1, str. 61-66
jezik rada: engleski
vrsta rada: neklasifikovan

Comparison elements on STG DICE cell for content-addressable memory and simulation of single-event transients
(naslov ne postoji na srpskom)
aNational Research Nuclear University MEPhI, Moscow Engineering Physics Institute, Moscow, Russia
bScientific Research Institute of System Analysis, Russian Academy of Sciences, Moscow, Russia



Project of the Russian Foundation for Basic Research: 14-29-09207


(ne postoji na srpskom)
Comparison elements on base the STG DICE cell and the logical element “Exclusive OR” for a content addressable memory were designed and simulated. The comparison element contains two identical joint groups of transistors that are spaced on the chip by the distance of four micrometers, so the loss of data in STG DICE cell practically excluded. On the characteristics of the new 65-nm CMOS comparison element, we predict the hardness of these item to single event rate (SER) more to hundred times compared to elements on 6-transistors cells and the standard DICE cell with distances 0.5-0.6 μm between mutually sensitive nodes.

Ključne reči


Abbas, S.M., Lee, S., Baeg, S., Park, S. (2014) An Efficient Multiple Cell Upsets Tolerant Content-Addressable Memory. IEEE Transactions on Computers, 63(8): 2094-2098
Frontini, L., Shojaii, S., Stabile, A., Liberali, V. (2012) A new XOR-based Content Addressable Memory architecture. u: 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012), Institute of Electrical and Electronics Engineers (IEEE), str. 701-704
Giot, D., Roche, P., Gasiot, G., Autran, J-L., Harboe-Sørensen, R. (2008) Heavy ion testing and 3D simulations of Multiple Cell Upset in 65nm standard SRAMs. IEEE Trans. Nucl. Sci, vol. 55, no. 4, pp. 2048-2054, Aug
Lee, H.-J. (2008) Immediate soft error detection using pass gate logic for content addressable memory. Electronics Letters, 44(4): 269
Loveless, T.D., Jagannathan, S., Reece, T., Chetia, J., Bhuva, B.L., McCurdy, M.W., Massengill, L.W., Wen, S., Wong, R., Rennie, D. (2011) Neutron- and Proton-Induced Single Event Upsets for D- and DICE-Flip/Flop Designs at a 40 nm Technology Node. IEEE Transactions on Nuclear Science, 58(3): 1008-1014
Pagiamtzis, K., Sheikholeslami, A. (2006) Content-Addressable Memory (CAM) Circuits and Architectures: A Tutorial and Survey. IEEE Journal of Solid-State Circuits, 41(3): 712-727
Pagiamtzis, K., Azizi, N., Najm, F. (2006) A Soft-Error Tolerant Content-Addressable Memory (CAM) Using An Error-Correcting-Match Scheme. u: IEEE Custom Integrated Circuits Conference 2006, Institute of Electrical and Electronics Engineers (IEEE), str. 301-304
Seifert, N., Gill, B., Foley, K., Relangi, P. (2008) Multi-cell upset probabilities of 45nm high-k + metal gate SRAM devices in terrestrial and space environments. u: 2008 IEEE International Reliability Physics Symposium, Institute of Electrical and Electronics Engineers (IEEE), str. 181-186
Stenin, V. Ya., Katunin, Yu. V., Stepanov, P. V. (2016) Upset-resilient RAM on STG DICE memory elements with the spaced transistors into two groups. Russian Microelectronics, 45(6): 419-432
Stenin, V. Ya. (2015) Simulation of the characteristics of the DICE 28-nm CMOS cells in unsteady states caused by the effect of single nuclear particles. Russian Microelectronics, 44(5): 324-334
Stenin, V. Ya., Stepanov, P. V. (2015) Basic memory elements using DICE cells for fault-tolerant 28 nm CMOS RAM. Russian Microelectronics, 44(6): 368-379
Stenin, V.Ya., Stepanov, P.V. (2017) The static RAM on DICE cells spaced onto two groups. u: 2017 International Siberian Conference on Control and Communications (SIBCON), Institute of Electrical and Electronics Engineers (IEEE), str. 1-6
Stenin, V.Ya., Antonyuk, A.V. (2016) Design of the 65-nm CMOS comparison element for a content-addressable memory and simulation of single-event transients. u: 2016 24th Telecommunications Forum (TELFOR), Institute of Electrical and Electronics Engineers (IEEE), str. 1-4
Uznanski, S., Gasiot, G., Roche, P., Tavernier, C., Autran, J. (2010) Single Event Upset and Multiple Cell Upset Modeling in Commercial Bulk 65-nm CMOS SRAMs and Flip-Flops. IEEE Transactions on Nuclear Science, 57(4): 1876-1883