Metrika članka

  • citati u SCindeksu: 0
  • citati u CrossRef-u:0
  • citati u Google Scholaru:[=>]
  • posete u poslednjih 30 dana:4
  • preuzimanja u poslednjih 30 dana:3
članak: 4 od 14  
Back povratak na rezultate
Journal of Applied Engineering Science
2019, vol. 17, br. 1, str. 26-34
jezik rada: engleski
vrsta rada: izvorni naučni članak
objavljeno: 04/07/2019
doi: 10.5937/jaes17-18539
Creative Commons License 4.0
One approach to compact testing of digital circuits
(naslov ne postoji na srpskom)
National Research Nuclear University "MEPhI", Institute of Cyber Intelligence Systems, Department of Computer Systems and Technologies, Moscow, Russian Federation

e-adresa: efber@mail.ru

Sažetak

(ne postoji na srpskom)
A problem of signature analyzer synthesis with required properties is solved for digital schemes compact testing. The main attention is devoted to the issues of eliminating losses of diagnostic information and to simplicity of structural organization. Solutions are based on detecting all error vectors or matrices resulting from failures of diagnostics objects related to the postulated class. Any other error vectors or matrices can be non-detectable and are excluded from consideration. For the compact testing of separate units of complex digital systems, the problem of synthesis of the generator structure that reproduces an assigned sequence of binary sets is being solved. Increased attention is given to issues of the non-excessive reproduction of sets sequence and structural organization simplicity. The solution is based on the application of a mathematical tool for linear sequence machines. A software implementation of the mathematical model is proposed. Error vectors or matrix detection process visualization AIDS are given. Additionally, means of the binary sets generation process visualization are presented.

Ključne reči

Reference

Ahmad, A., Al-Abri, D. (2012) Adding pseudo-random test sequence generator in the test simulator for DFT approach. Journal of Computer Technology and Applications (JCTA), 3(7), 463-470
Baida, I.P., Semerenko, V.P. (1981) Sintez linejnoj posledovatel'nostnoj mashiny, vosproizvodjashhej zadannuju posledovatel'nost' dvoichnyh naborov [Synthesis of a linear sequential machine that reproduces a given sequence of binary sets]. Jelektronnoe modelirovanie [Electronic modeling], No. 5, pp, 65-70
Berezkin, E.F. (2018) Design of signature analyzer structures with required properties. ARPN Journal of Engineering and Applied Sciences, Volume 13, Number 8, p. 2850-2854
Berezkin, E.F. (2012) Nadezhnost' i tekhnicheskaya diagnostika sistem: Uchebnoe posobie [Reliability and technical diagnostics systems: The manual]. Moskva: NRNU MEPhI, Ser. Biblioteka jadernogo universiteta [The library of nuclear university], p.244
Brglez, F. (1984) On testability analysis of combinational networks. u: Circuits and Systems, International Symp, May 1984, Proc
Daehn, W., Mucha, J. (1981) Hardware test pattern generation for built-in testing. u: Intern Test Conf., Philadelphia, oct., pp.110-113
David, R. (1984) Signature analysis of multi-output circuits. u: International Fault-Tolerant Computing Symp., June 1984, Proc, 366-371
Gill, A. (1974) Linejnye posledovatel'nostnye mashiny: Analiz, sintez i primenenie [Linear sequential circuits: Analysis, synthesis and applications]. Moskva: Nauka, 288-288
Goessel, M., Chakrabarty, K., Ocheretnij, V., Leininger, A. (2004) A signature analysis technique for the identification of failing vectors with application to scan-BIST. Journal of Electronic Testing: Theory and Applications, 20(6), 611-622
Goryashko, A.P. (1987) Sintez diagnostiruemyh skhem vychislitel'nyh ustrojstv [Synthesis diagnosed circuits computing devices]. Moskva: Nauka, 288
Hassen, S.Z., McCluskey, E.J. (1984) Increased fault coverage through multiple signatures. u: International Fault-Tolerant Computing Symp., June 1984, Proc, 354-359
Khade, R., Gourkar, S. (2013) Fault testing of CMOS integrated circuits using signature analysis method. International Journal of Application or Innovation in Engineering & Management (IJAIEM), Vol. 2, Issue 5, May, pp. 73-82
Kinoshita, K., Saluja, K.K. (1986) Built-in testing of memory using an on-chip compact testing scheme. IEEE Trans. on Computers, vol. C-35, no. 10, Oct., pp. 862-870
Lancaster, P., Tismenetsky, M. (1985) The theory of matrices. New York: Academic Press, 570-570
Litikov, I.P. (1990) Kol'cevoe testirovanie cifrovyh ustrojstv [Circuit testing of digital devices]. Moskva: Energoatomisdat, 157-157