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Telfor Journal
2019, vol. 11, br. 1, str. 41-45
jezik rada: engleski
vrsta rada: neklasifikovan
doi:10.5937/telfor1901041P


FIR filter implementation for high-performance application in a high-end FPGA
(naslov ne postoji na srpskom)
aRT-RK Institute for Computer Based Systems, Novi Sad
bUniverzitet u Novom Sadu, Fakultet tehničkih nauka

e-adresa: stefan.pijetlovic@rtrk.com, milos.subotic@rtrk.com, vladimir.marinkovic@rt-rk.com , pjeva@uns.ac.rs

Projekat

Razvoj metodologije i softvera za procenu kvaliteta video signala u multimedijalnim sistemima (MPNTR - 32029)

Sažetak

(ne postoji na srpskom)
In this paper a high-performance application which uses multiple 48k tap FIR filters is presented. Due to its size, complexity and restrictions such as real-time, small latency and large memory bandwidth, the filter was implemented in UltraScale+, a high-end FPGA from Xilinx. The system was verified using a gold reference model written in C (high-level algorithm verification) and an analytical model calculated manually. The system was also tested using a development board and SystemVerilog (for register-transfer level and timing verification). The obtained results show a perfect match between the reference models and the actual output. The main novelty of the paper is the implementation of such an immense real-time signal processing system based on FIR filters consisting of over a million taps all together in a single design spread out across a chip containing three dies. Details about the resources allocated within the FPGA are also given in a table in the results chapter.

Ključne reči

Reference

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