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2020, vol. 18, br. 4, str. 515-519
Modeling of NBTI degradation in p-channel VDMOSFETs
(naslov ne postoji na srpskom)
aUniverzitet u Nišu, Elektronski fakultet, Katedra za mikroelektroniku
bSrpska akademija nauke i umetnosti (SANU), Beograd

e-adresanikola.i.mitrovic@elfak.ni.ac.rs
Projekat:
Karakterizacija, analiza i modelovanje fizičkih pojava u tankim slojevima za primenu u MOS nanokomponentama (MPNTR - 171026)
Razvoj, optimizacija i primena tehnologija samonapajajućih senzora (MPNTR - 32026)
Work has also been supported by Serbian Academy of Sciences and Arts (SASA) under grant: Effects of combined stressing in modern microelectronical circuits (multistress), (grant no. F-148.)

Ključne reči: reliability; VDMOS power transistors; threshold voltage; modeling
Sažetak
(ne postoji na srpskom)
This paper gives insight in reliability of p-channel VDMOSFET power transistors subjected to NBT stressing. Effects that lead to degradation of characteristics of these electronic circuits are presented, out of which threshold voltage shift with NBT stressing is further analysed. Measurements have been done and experimental results of the threshold voltage degradation of power transistors IRF9520 caused by different types of negative bias temperature stressing are shown. Stressing types, both static and pulsed, and their impact on transistors, especially on threshold voltage shifts have been explained in more details. An elementary equivalent electrical circuit is designed and proposed with the goal to model impact of both types of stressing, and also to calculate and estimate reliability of the circuit under specified stress. All of the elements of the modeling circuit and their dependencies are explained. Example of modeling from the experimental data is given together with the comparison between measured and modeled results. Differences between obtained results are discussed.
Reference
Danković, D., Manić, I., Stojadinović, N., Prijić, Z., Đorić-Veljković, S., Davidović, V., Prijić, A., Paskaleva, A., Spassov, D., Golubović, S. (2017) Modelling of threshold voltage shift in pulsed NBT stressed P-channel power VDMOSFETs. u: 2017 IEEE International Conference on Microelectronics (MIEL) (30th), Proceedings, IEEE, 147-151
Danković, D., Manić, I., Đorić-Veljković, S., Davidović, V., Golubović, S., Stojadinović, N. (2006) NBT stress-induced degradation and lifetime estimation in p-channel power VDMOSFETs. Microelectronics Reliability, 46(9-11): 1828-1833
Danković, D., Stojadinović, N., Prijić, Z., Manić, I., Davidović, V., Prijić, A., Djorić-Veljković, S., Golubović, S. (2015) Analysis of recoverable and permanent components of threshold voltage shift in NBT stressed p-channel power VDMOSFET. Chinese Physics B, 24(10): 106601-106601
Danković, D., Mitrović, N., Prijić, Z., Stojadinović, N.D. (2020) Modeling of NBTS Effects in P-Channel Power VDMOSFETs. IEEE Transactions on Device and Materials Reliability, 20(1): 204-213
Danković, D., Manić, I., Davidović, V., Prijić, A., Marjanović, M., Ilić, A., Prijić, Z., Stojadinović, N.D. (2016) On the Recoverable and Permanent Components of NBTI in p-Channel Power VDMOSFETs. IEEE Transactions on Device and Materials Reliability, 16(4): 522-531
Davidović, V., Danković, D., Ilić, A., Manić, I., Golubović, S., Đorić-Veljković, S., Prijić, Z., Stojadinović, N. (2016) NBTI and Irradiation Effects in P-Channel Power VDMOS Transistors. IEEE Transactions on Nuclear Science, 63(2): 1268-1275
Khovanski, A.G. (1998) Geometry of Differential Equations. American Mathematical Society
Mahapatra, S., Goel, N., Desai, S., Gupta, S., Jose, B., Mukhopadhyay, S., Joshi, K., Jain, A., Islam, A.E., Alam, M.A. (2013) A Comparative Study of Different Physics-Based NBTI Models. IEEE Transactions on Electron Devices, 60(3): 901-916
Mahapatra, S., Alam, M.A., Bharath, K.P., Dalei, T.R., Varghese, D., Saha, D. (2005) Negative Bias Temperature Instability in CMOS Devices. Microelectronic Engineering, 80: 114-121
Mitrović, N., Danković, D., Prijić, Z., Stojadinović, N. (2019) Modelling of DVT in NBT Stressed P-Channel Power VDMOSFETs. u: 2019 IEEE International Conference on Microelectronics (MIEL) (31st), Proceedings, IEEE, 177-180
Ogawa, S., Shimaya, M., Shiono, N. (1995) Interface-trap generation at ultrathin SiO2 (4-6 nm)-Si interfaces during negative-bias temperature aging. Journal of Applied Physics, 77(3): 1137
Prijić, A., Danković, D., Vračar, Lj., Manić, I., Prijić, Z., Stojadinović, N. (2012) A method for negative bias temperature instability (NBTI) measurements on power VDMOS transistors. Measurement Science and Technology, 23(8): 085003-085003
Reisinger, H., Grasser, T., Gustin, W., Schlunder, C. (2010) The statistical analysis of individual defects constituting NBTI and its implications for modeling DC- and AC-stress. u: 2010 IEEE International Reliability Physics Symposium, IEEE, 7-15
Stathis, J.H., Zafar, S. (2006) The negative bias temperature instability in MOS devices: A review. Microelectronics Reliability, 46(2-4): 270-286
Stojadinović, N., Danković, D., Đorić-Veljković, S., Davidović, V., Manić, I., Golubović, S. (2005) Negative bias temperature instability mechanisms in p-channel power VDMOSFETs. Microelectronics Reliability, 45(9-11): 1343-1348
 

O članku

jezik rada: engleski
vrsta rada: izvorni naučni članak
DOI: 10.5937/jaes0-26760
primljen: 26.05.2020.
prihvaćen: 02.09.2020.
objavljen u SCIndeksu: 25.12.2020.
metod recenzije: dvostruko anoniman
Creative Commons License 4.0

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